1. Field of the Invention
The present invention relates generally to semiconductor devices and semiconductor memory devices, and more specifically, to a semiconductor device and a semiconductor memory device permitting use of a redundant circuit to be easily detected externally.
The invention has particular applicability to Dynamic Random Access Memories (DRAMs).
2. Description of the Background Art
In recent years, higher reliability in manufacturing has been in demand, as the integration density of semiconductor integrated circuit devices increases. Meanwhile, in order to improve yield in manufacturing of semiconductor integrated circuit devices, a redundant circuit is generally provided in a semiconductor integrated circuit device. Particularly, semiconductor memories such as Dynamic Random Access Memories (hereinafter referred to as "DRAMs") and Static Random Access Memories (hereinafter referred to as "SRAMs") which have high integration densities for achieving large storage capacities are provided with redundant circuits.
Generally, a redundant circuit is provided in a semiconductor integrated circuit device to functionally replace a defective circuit found in the device. More specifically, the redundant circuit is activated by fusing a fuse element provided in the semiconductor integrated circuit device, so that the redundant circuit is operated in place of the defective circuit.
When the presence of some failure is recognized in the semiconductor integrated circuit device, the position (or location) of the failure must be specified. The operation of locating the failure, however, would be different depending upon if the redundant circuit is activated or not. Accordingly, it is necessary to externally detect the presence/absence of activation (or use) of the redundant circuit. The following conventional techniques are known for this purpose.
FIG. 20 is a diagram showing one example of a conventional redundant use detection circuit. Referring to FIG. 20, redundant use detection circuit 58 is connected to some input terminal or a predetermined input terminal 37. Redundant use detection circuit 58 includes a fuse element FS, and NMOS transistors Q31 and Q32 connected in series between terminal 37 and ground potential. Transistors Q31 and Q32 are each provided in a diode-connected manner.
When a redundant circuit (not shown) is not being used, in other words when the redundant circuit is not activated, fuse element FS is left. Meanwhile, when the redundant circuit is being used, in other words when the redundant circuit is activated, fuse FS is fused by externally applied voltage or a laser beam.
Therefore, detection of the presence/absence of use of such a redundant circuit can be conducted by applying high voltage to terminal 37. More specifically, high voltage is supplied to terminal 37 from a high voltage source 142, and an amperemeter 141 detects the presence of current flowing cross terminal 37 and detects use of the redundant circuit. For the high voltage, a voltage level enough for turning on transistors Q31 and Q32 each of which operates as a diode is selected.
When, for example, the redundant circuit is not being used, current flows across fuse element FS, and transistors Q31 and Q32 by supplying high voltage. Meanwhile, if the redundant circuit is used, since fuse element FS is cut off, current does not flow across terminal 37. Accordingly, one can know the presence of current flowing across terminal 37 using amperemeter 141. In other words, the presence/absence of the use of the redundant circuit can be externally known using amperemeter 141.
FIG. 21 is a diagram showing another example of a conventional redundant use detection circuit. Redundant use detection circuit 59 shown in FIG. 21 is disclosed in U.S. Pat. No. 4,480,199. Also in this redundant use detection circuit 59, high voltage is applied across an external terminal TTLPN, and different current flows by connecting or disconnecting fuse element FS. Fuse element FS shown in FIG. 21 is left or disconnected based on the presence/absence of the use of the redundant circuit, and therefore the present/absence of the use of the redundant circuit can be detected by detecting the presence/absence of current flowing across external terminal TTLP.sub.IN.
FIG. 23 is a block diagram showing a semiconductor memory using a conventional redundant use detection circuit. The circuit shown in FIG. 23 is disclosed in Japanese Patent Laying-Open No. 62-22300.
Referring to FIG. 23, a memory cell array 101 includes memory cells MC connected between bit lines 103 and 104. A memory cell MC is selected in response to an activation signal on a word line 102. A redundant memory cell column 105 is provided at an end of memory cell array 105. Redundant memory cell column 105 also includes memory cells connected to bit lines and word lines.
Address buffers 111 to 11n receive externally applied address signals Aa to An. Program elements 131 to 13n are provided for programming address in a defective memory cell column. A Y decoder 108 decodes address signals Aa to An, and selects one column to be accessed through a selector circuit 104. A data signal read out from a memory cell is output through an output buffer 107.
A redundant use detection circuit 60 includes NMOS transistors 121, 122, and 125, and a high resistance element 123. An amperemeter 141 and a high voltage source 142 are connected between an external terminal 126 and ground potential.
If a defective memory cell column is present in memory cell array 101, the address of the defective memory cell column is programmed by selectively disconnecting program elements 131 to 13n. Accordingly, when address signals Aa to An requesting accessing to the defective memory cell column are externally applied, program elements 131 to 13n output a signal SR for selecting a redundant memory cell column. Signal SR is also applied to redundant use detection circuit 60. Transistor 121 receives signal SR through a gate electrode.
The presence/absence of use of the redundant circuit in the semiconductor memory shown in FIG. 23 is detected externally as in the following manner. Amperemeter 141 and high voltage source 142 are connected to external terminal 126. Then, address signals Aa to An which sequentially change are applied through address buffers 111 to 11n. Assuming that the address of the defective memory cell column is programmed by selectively disconnecting program elements 131 to 13n, when address signals Aa-An requesting accessing to the defective memory column are applied, redundant memory cell column access signal SR is output from program elements 131 to 13n.
In response to signal SR, transistor 131 is turned off, while transistor 122 is turned on. Therefore, current flows from high voltage source 141 across terminal 126, transistors 125 and 122 toward power supply V.sub.DD. The use of the redundant circuit can be detected by detecting this current using amperemeter 141.
Meanwhile, if the redundant circuit is not being used, redundant memory cell column selection signal SR is not output from program elements 131 to 13n, if any of address signals Aa to An is applied. Transistor 121 therefore continues to conduct, while transistor 122 continues to be off. As described above, since resistance element 123 has a high resistance value and transistor 122 is turned off, current does not flow across terminal 126, which can be detected through amperemeter 141.
FIG. 22 is a diagram showing a further example of a conventional redundant use detection circuit. The above-described Japanese Patent Laying-Open No. 62-22300 discloses that a redundant use detection circuit 61 shown in FIG. 22 can be used in place of redundant use detection circuit 60 shown in FIG. 23. Redundant use detection circuit 61 uses a capacitor 127 in place of resistance element 123 shown in FIG. 23. Use of circuit 61 also permits detection of the presence/absence of use of a redundant circuit as in the case of circuit 60 shown in FIG. 23.
Use of redundant use detection circuits 58 to 61 shown in FIGS. 20 to 23 in a semiconductor integrated circuit device is however encountered with the following disadvantage.
Redundant use detection circuits 58 and 59 shown in FIGS. 20 and 21 each include fuse element FS for indicating the presence/absence of use of a redundant circuit. More specifically, not only a fuse element for programming in the redundant circuit, but also such an additional fuse element FS is provided in redundant use detection circuits 58 and 59. Generally, when a fuse element is fused, the peripheral circuitry is adversely affected by thermal damages and spreading of fused material. Accordingly, in order to prevent such adverse effects, in design, other wirings and transistors are not provided in a circle with the radius of about 10 .mu.m around a fuse element. Stated differently, providing a fuse element indicating the presence/absence of use of a redundant circuit impairs high density integration.
In addition, when fuse element FS is left in redundant use detection circuits 58 and 59 shown in FIGS. 20 and 21, very small current flows across the fuse element. More specifically, even when high voltage for testing is not applied in a normal operation, current does flow into redundant use detection circuits 58 and 59. This means an additional load for another semiconductor integrated circuit device connected to external terminal 37 (or TTLP.sub.IN).
Furthermore, when redundant use detection circuits 60 and 61 shown in FIGS. 22 and 23 are used, address signals Aa to An to specify all the memory cell columns should be sequentially applied in order detect the presence/absence of use of the redundant circuit. Therefore, a long time period and supply of complicated control signals are necessary for detecting the presence/absence of use of the detection circuit.
It is one object of the invention to improve integration density in a semiconductor device and a semiconductor memory device permitting external detection of use of a redundant circuit.
Another object of the invention is to reduce current flowing across an external terminal in a normal operation mode in a semiconductor device and a semiconductor memory device permitting external detection of use of a redundant circuit.
A still further object of the invention is to reduce a time period necessary for detecting use of redundant circuit in a semiconductor device and semiconductor memory device permitting external detection of use of a redundant circuit.